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MC145482 motorola 1 product preview
the MC145482 is a 13bit linear pcm codecfilter with 2s complement data format, and is offered in 20pin sog and ssop packages. this device performs the voice digitization and reconstruction as well as the band limiting and smoothing required for the voice coding in digital communication systems. this device is designed to operate in both synchronous and asynchronous applications and contains an onchip precision reference voltage. this device has an input operational amplifier whose output is the input to the encoder section. the encoder section immediately lowpass filters the analog signal with an active rc filter to eliminate very high frequency noise from being modulated down to the passband by the switched capacitor filter. from the active rc filter, the analog signal is converted to a differential signal. from this point, all analog signal processing is done differentially. this allows processing of an analog signal that is twice the amplitude allowed by a singleended design, which reduces the significance of noise to both the inverted and noninverted signal paths. another advantage of this differential design is that noise injected via the power supplies is a commonmode signal that is cancelled when the inverted and noninverted signals are recombined. this dramatically improves the power supply rejection ratio. after the differential converter, a differential switched capacitor filter band passes the analog signal from 200 hz to 3400 hz before the signal is digitized by the differential 13bit linear a/d converter. the digital output is 2s complement format. the decoder digital input accepts 2s complement data and reconstructs it using a differential 13bit linear d/a converter. the output of the d/a is lowpass filtered at 3400 hz and sinx/x compensated by a differential switched capacitor filter. the signal is then filtered by an active rc filter to eliminate the outofband energy of the switched capacitor filter. the MC145482 pcm codecfilter has a high impedance v ag reference pin which allows for decoupling of the internal circuitry that generates the midsupply v ag reference voltage to the v ss power supply ground. this reduces clock noise on the analog circuitry when external analog signals are referenced to the power supply ground. the MC145482 13bit linear pcm codecfilter accepts both short frame sync and long frame sync clock formats, and utilizes cmos due to its reliable lowpower performance and proven capability for complex analog/digital vlsi functions. ? single 5 v power supply ? 13bit linear adc/dac conversions with 2s complement data format ? typical power dissipation of 25 mw, powerdown of 0.01 mw ? fullydifferential analog circuit design for lowest noise ? transmit bandpass and receive lowpass filters onchip ? transmit highpass filter may be bypassed by pin selection ? active rc prefiltering and postfiltering ? onchip precision reference voltage of 1.575 v for a 0 dbm tlp @ 600 w ? fullduplex sample rates from 7 k to 16 k samples/s ? 3terminal input op amp can be used, or a 2channel input multiplexer ? receive gain control from 0 db to 21 db in 3 db steps in synchronous operation ? pushpull 300 w power drivers with external gain adjust this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. order this document by MC145482/d semiconductor technical data pin assignment dw suffix sog package case 751d ordering information MC145482dw sog package MC145482sd ssop 20 1 v dd po pi ro v ag ref pdi bclkr dr fsr po+ 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 hb tg ti ti+ v ag mclk bclkt dt fst v ss sd suffix ssop case 940c 20 1 ? motorola, inc. 1997 rev 0 3/97 tn97032700
MC145482 motorola 2 freq freq ro pi po po + v dd v ss v ag tg ti ti + + 1 1 + shared dac dac 1.575 v ref adc transmit shift register sequence and control dr fsr bclkr pdi mclk bclkt fst dt receive shift register hb v ag ref v dd v ss r* r* figure 1. MC145482 13bit linear pcm codecfilter block diagram device description a pcm codecfilter is used for digitizing and reconstruct- ing the human voice. these devices are used primarily for the telephone network to facilitate voice switching and trans- mission. once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (t1, microwave, satellites, etc.) without degradation. the name codec is an acronym from ``coder'' for the analogtodigital converter (adc) used to digitize voice, and ``decoder'' for the digitaltoanalog converter (dac) used for reconstruct- ing voice. a codec is a single device that does both the adc and dac conversions. to digitize intelligible voice requires a signaltodistortion ratio of about 30 db over a dynamic range of about 40 db. this may be accomplished with a linear 13bit adc and dac. the MC145482 satisfies these requirements and may be used as the analog frontend for voice coders using dsp technology to further compress the digital data stream. in a sampling environment, nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal's highest frequency component. voice contains spectral energy above 3 khz, but its absence is not detrimental to intelligibility. to reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 khz was adopted, consistent with a band- width of 3 khz. this sampling requires a lowpass filter to limit the high frequency energy above 3 khz from distorting the inband signal. the telephone line is also subject to 50/60 hz power line coupling, which must be attenuated from the signal by a highpass filter before the analogto digital converter. the MC145482 includes a highpass filter for compatibility with existing telephone applications, but it may be removed from the analog input signal path by the highpass bypass pin. the digitaltoanalog conversion process reconstructs a staircase version of the desired inband signal, which has spectral images of the inband signal modulated about the sample frequency and its harmonics. these spectral images are called aliasing components, which need to be attenuated to obtain the desired signal. the lowpass filter used to at- tenuate these aliasing components is typically called a re- construction or smoothing filter. the MC145482 pcm codecfilter has the codec, both presampling and reconstruction filters, and a precision volt- age reference onchip.
MC145482 motorola 3 pin descriptions power supply v dd positive power supply (pin 6) this is the most positive power supply and is typically con- nected to + 5 v. this pin should be decoupled to v ss with a 0.1 m f ceramic capacitor. v ss negative power supply (pin 15) this is the most negative power supply and is typically connected to 0 v. v ag analog ground output (pin 20) this output pin provides a midsupply analog ground. this pin should be decoupled to v ss with a 0.01 m f ceramic ca- pacitor. all analog signal processing within this device is ref- erenced to this pin. if the audio signals to be processed are referenced to v ss , then special precautions must be utilized to avoid noise between v ss and the v ag pin. refer to the ap- plications information in this document for more information. the v ag pin becomes high impedance when this device is in the powereddown mode. v ag ref analog ground reference bypass (pin 1) this pin is used to capacitively bypass the onchip circuit- ry that generates the midsupply voltage for the v ag output pin. this pin should be bypassed to v ss with a 0.1 m f ceram- ic capacitor using short, low inductance traces. the v ag ref pin is only used for generating the reference voltage for the v ag pin. nothing is to be connected to this pin in addition to the bypass capacitor. all analog signal processing within this device is referenced to the v ag pin. if the audio signals to be processed are referenced to v ss , then special precautions must be utilized to avoid noise between v ss and the v ag pin. refer to the applications information in this document for more information. when this device is in the powereddown mode, the v ag ref pin is pulled to the v dd power supply with a nonlinear, highimpedance circuit. control hb transmit highpass filter bypass (pin 16) this pin selects whether the transmit highpass filter will be used or bypassed, which allows frequencies below 200 hz to appear at the input of the adc to be digitized. this highpass filter is a third order filter for attenuating power line frequencies, typically 50/60 hz. a logic low selects this filter. a logic high deselects or bypasses this filter. when the filter is bypassed, the transmit frequency response extends down to dc. pdi powerdown input (pin 10) this pin puts the device into a low power dissipation mode when a logic 0 is applied. when this device is powered down, all of the clocks are gated off and all bias currents are turned off, which causes ro, po, po+, tg, v ag , and dt to be- come high impedance. the device will operate normally when a logic 1 is applied to this pin. the device goes through a powerup sequence when this pin is taken to a logic 1 state, which prevents the dt pcm output from going low im- pedance for at least two fst cycles. the v ag and v ag ref circuits and the signal processing filters must settle out be- fore the dt pcm output or the ro receive analog output will represent a valid analog signal. analog interface ti+ transmit analog input (noninverting) (pin 19) this is the noninverting input of the transmit input gain setting operational amplifier. this pin accommodates a differ- ential to singleended circuit for the input gain setting op amp. this allows input signals that are referenced to the v ss pin to be level shifted to the v ag pin with minimum noise. this pin may be connected to the v ag pin for an inverting amplifier configuration if the input signal is already refer- enced to the v ag pin. the common mode range of the ti+ and ti pins is from 1.2 v, to v dd minus 1.2 v. this is an fet gate input. the ti+ pin also serves as a digital input control for the transmit input multiplexer. connecting the ti+ pin to v dd will place this amplifier's output (tg) into a highimpedance state, and selects the tg pin to serve as a highimpedance input to the transmit filter. connecting the ti+ pin to v ss will also place this amplifier's output (tg) into a highimpedance state, and selects the ti pin to serve as a highimpedance input to the transmit filter. ti transmit analog input (inverting) (pin 18) this is the inverting input of the transmit gain setting op- erational amplifier. gain setting resistors are usually con- nected from this pin to tg and from this pin to the analog signal source. the common mode range of the ti+ and ti pins is from 1.2 v to v dd 1.2 v. this is an fet gate input. the ti pin also serves as one of the transmit input mulit- plexer pins when the ti+ pin is connected to v ss . when ti+ is connected to v dd , this pin is ignored. see the pin descrip- tions for the ti+ and the tg pins for more information. tg transmit gain (pin 17) this is the output of the transmit gain setting operational amplifier and the input to the transmit bandpass filter. this op amp is capable of driving a 2 k w load. connecting the ti+ pin to v dd will place the tg pin into a highimpedance state, and selects the tg pin to serve as a highimpedance input to the transmit filter. all signals at this pin are referenced to the v ag pin. when ti+ is connected to v ss , this pin is ignored. see the pin descriptions for ti+ and ti pins for more in- formation. this pin is high impedance when the device is in the powereddown mode. ro receive analog output (inverting) (pin 2) this is the inverting output of the receive smoothing filter from the digitaltoanalog converter. this output is capable of driving a 2 k w load to 1.575 v peak referenced to the v ag pin. if the device is operated halfchannel with the fst pin clocking and fsr pin held low, the receive filter input will be
MC145482 motorola 4 connected to the v ag voltage. this minimizes transients at the ro pin when fullchannel operation is resumed by clocking the fsr pin. this pin is high impedance when the device is in the powereddown mode. pi power amplifier input (pin 3) this is the inverting input to the po amplifier. the non inverting input to the po amplifier is internally tied to the v ag pin. the pi and po pins are used with external resis- tors in an inverting op amp gain circuit to set the gain of the po+ and po pushpull power amplifier outputs. connect- ing pi to v dd will power down the power driver amplifiers and the po+ and po outputs will be high impedance. po power amplifier output (inverting) (pin 4) this is the inverting power amplifier output, which is used to provide a feedback signal to the pi pin to set the gain of the pushpull power amplifier outputs. this pin is capable of driving a 300 w load to po+. the po+ and po outputs are differential (pushpull) and capable of driving a 300 w load to 3.15 v peak, which is 6.3 v peaktopeak. the bias voltage and signal reference of this output is the v ag pin. the v ag pin cannot source or sink as much current as this pin, and therefore low impedance loads must be between po+ and po. the po+ and po differential drivers are also capable of driving a 100 w resistive load or a 100 nf piezoelectric transducer in series with a 20 w resister with a smalll in- crease in distortion. these drivers may be used to drive re- sistive loads of 32 w when the gain of po is set to 1/4 or less. connecting pi to v dd will power down the power driver amplifiers, and the po+ and po outputs will be high imped- ance. this pin is also high impedance when the device is powered down by the pdi pin. po+ power amplifier output (noninverting) (pin 5) this is the noninverting power amplifier output, which is an inverted version of the signal at po. this pin is capable of driving a 300 w load to po. connecting pi to v dd will power down the power driver amplifiers and the po+ and po outputs will be high impedance. this pin is also high im- pedance when the device is powered down by the pdi pin. see pi and po for more information. digital interface mclk master clock (pin 11) this is the master clock input pin. the clock signal applied to this pin is used to generate the internal 256 khz clock and sequencing signals for the switchedcapacitor filters, adc, and dac. the internal prescaler logic compares the clock on this pin to the clock at fst (8 khz) and will automatically accept 256, 512, 1536, 1544, 2048, 2560, or 4096 khz. for mclk frequencies of 256 and 512 khz, mclk must be syn- chronous and approximately rising edge aligned to fst. for optimum performance at frequencies of 1.536 mhz and higher, mclk should be synchronous and approximately ris- ing edge aligned to the rising edge of fst. in many ap- plications, mclk may be tied to the bclkt pin. fst frame sync, transmit (pin 14) this pin accepts an 8 khz clock that synchronizes the out- put of the serial pcm data at the dt pin. this input is com- patible with both long frame sync and short frame sync. if both fst and fsr are held low for several 8 khz frames, the device will power down. fst must be clocking for the device to power up affter being powered down by the frame syncs. bclkt bit clock, transmit (pin 12) this pin controls the transfer rate of transmit pcm data. in the synchronous modes of signbit extended and receive gain adjust, the bclkt also controls the transfer rate of the receive pcm data. this pin can accept any bit clock frequen- cy from 256 to 4096 khz for long frame sync and short frame sync timing. dt data, transmit (pin 13) this pin is controlled by fst and bclkt and is high im- pedance except when outputting pcm data. this pin is high impedance when the device is in the powereddown mode. fsr frame sync, receive (pin 7) this pin accepts an 8 khz clock, which synchronizes the input of the serial pcm data at the dr pin. fsr can be asynchronous to fst in the long frame sync or short frame sync modes. bclkr bit clock, receive (pin 9) this pin accepts any bit clock frequency from 256 to 4096 khz. the bclkr pin is also used as a mode select pin when not being clocked for several 8 khz frames. the bcklt pin is used to clock the receive pcm data transfers when the bclkr pin is not being clocked. when the bclkr pinis a logic 0, the signbit extended synchronous mode is selected, which uses 16bit transfers with the first four bits being the sign bit. when the bclkr pin is a logic 1, the receive gain adjust synchronous mode is selected, which uses a 13bit transfer for the transmit pcm data, but uses a 16bit transfer for the receive side, with the 13bit voice data being first, fol- lowed by three bits which control the attenuation of the re- ceive analog output. dr data, receive (pin 8) this pin is the pcm data input. see the pin descriptions for fsr, bclkr, and bcklt for more information.
MC145482 motorola 5 functional description analog interface and signal path the transmit portion of this device includes a lownoise, threeterminal op amp capable of driving a 2 k w load. this op amp has inputs of ti+ (pin 19) and ti (pin 18) and its output is tg (pin 17). this op amp is intended to be confi- gured in an inverting gain circuit. the analog signal may be applied directly to the tg pin if this transmit op amp is inde- pendently powered down by connecting the ti+ input to the v dd power supply. the tg pin becomes high impedance when the transmit op amp is powered down. the tg pin is internally connected to a 3pole antialiasing prefilter. this prefilter incorporates a 2pole butterworth active lowpass filter, followed by a single passive pole. this prefilter is fol- lowed by a singleended to differential converter that is clocked at 512 khz. all subsequent analog processing uti- lizes fullydifferential circuitry. the next section is a fullydif- ferential, 5pole switchedcapacitor lowpass filter with a 3.4 khz frequency cutoff. after this filter is a 3pole switchedcapacitor highpass filter having a cutoff fre- quency of about 200 hz. this highpass stage has a trans- mission zero at dc that eliminates any dc coming from the analog input or from accumulated op amp offsets in the pre- ceding filter stages. the highpass filter may be bypassed or removed from the signal path by the hb pin. when the high pass filter is bypassed, the frequency response extends down to include dc. the last stage of the highpass filter is an autozeroed sample and hold amplifier. one bandgap voltage reference generator and digitalto analog converter (dac) are shared by the transmit and re- ceive sections. the autozeroed, switchedcapacitor bandgap reference generates precise positive and negative reference voltages that are virtually independent of tempera- ture and power supply voltage. a capacitor array (cdac) is combined with a resistor string (rdac) to implement the 13bit linear dac structure. the encode process uses the dac, the voltage reference, and a framebyframe auto- zeroed comparator to implement a successive approxima- tion conversion algorithm. all of the analog circuitry involved in the data conversion (the voltage reference, rdac, cdac, and comparator) are implemented with a differential architec- ture. the receive section includes the dac described above, a sample and hold amplifier, a 5pole, 3400 hz switched ca- pacitor lowpass filter with sinx/x correction, and a 2pole active smoothing filter to reduce the spectral components of the switched capacitor filter. the output of the smoothing fil- ter is buffered by an amplifier, which is output at the ro pin. this output is capable of driving a 2 k w load to the v ag pin. the MC145482 also has a pair of power amplifiers that are connected in a pushpull configuration. the pi pin is the in- verting input to the po power amplifier. the noninverting input is internally tied to the v ag pin. this allows this amplifier to be used in an inverting gain circuit with two external resis- tors. the po+ a mplifier has a gain of minus one, and is in- ternally connected to the po output. this complete power amplifier circuit is a differential (pushpull) amplifier with ad- justable gain. the power amplifier may be powered down in- dependently of the rest of the chip by connecting the pi pin to v dd . the calibration level for both adc and dac of this 13bit linear pcm codecfilter is referenced to mulaw with the same bit voltage weighting about the zero crossing. this re- sults in the 0 dbm0 calibration level being 3.20 db below the peak sinusoidal level before clipping. based on the reference voltage of 1.575 v, the calibration level is 0.775 vrms or 0 dbm at 600 w . the MC145482 has the ability to attenuate the receive analog output when used in the receive gain adjust mode. this mode is accessed by applying a logic high to the bclkr pin while the rest of the clock pins are clocked nor- mally. this allows three additional bits that will be used to control the gain of the analog output to be clocked into the dr pin following the 13 bits of voice data. table 1 shows the attenuation values and the corresponding digital codes. table 1. receive gain adjust mode coefficients and attenuation weightings coefficient attenuation in db 000 0 001 3 010 6 011 9 100 12 101 15 110 18 111 21 powerdown there are two methods of putting this device into a low power consumption mode, which makes the device nonfunc- tional and consumes virtually no power. pdi is the power down input pin which, when taken low, powers down the device. another way to power the device down is to hold both the fst and fsr pins low while the bclkt and mclk pins are clocked. when the chip is powered down, the v ag , tg, ro, po+, po, and dt outputs are high impedance and the v ag ref pin is pulled to the v dd power supply with a non linear, highimpedance circuit. to return the chip to the pow- erup state, pdi must be high and the fst frame sync pulse must be present while the bclkt and mclk pins are clocked. the dt output will remain in a highimpedance state for at least two 8 khz fst pulses after powerup. master clock since this codecfilter design has a single dac architec- ture, the mclk pin is used as the master clock for all analog signal processing including analogtodigital conversion, digitaltoanalog conversion, and for transmit and receive fil- tering functions of this device. the clock frequency applied to the mclk pin may be 256 khz, 512 khz, 1.536 mhz, 1.544 mhz, 2.048 mhz, 2.56 mhz, or 4.096 mhz. this de- vice has a prescaler that automatically determines the proper divide ratio to use for the mclk input, which achieves the re- quired 256 khz internal sequencing clock. the clocking re- quirements of the mclk input are independent of the pcm data transfer mode (i.e., long frame sync, short frame sync, whether the device is used in the synchronous modes or not).
MC145482 motorola 6 digital i/o the MC145482 is a 13bit linear device using 2s comple- ment data format. table 2 shows the 13bit data word format for the maximum positive code and negative zero and full scale. table 3 shows the series of eight 13bit pcm words that correspond to a digital milliwatt. the digital milliwatt is the 1 khz calibration signal reconstructed by the dac that de- fines the absolute gain or 0 dbm0 transmission level point (tlp) of the dac. the calibration level for this 13bit linear adc and dac is referenced to mulaw with the same bit voltage weighting about the zero crossing. this results in the 0 dbm0 calibration level being 3.20 db below the peak sinu- soidal level before clipping. refer to figures 2a2d for a summary and comparison of the four pcm data interface modes of this device. table 2. pcm codes for zero and fullscale level sign bit magnitude bits + full scale 0 1111 1111 1111 + one step 0 0000 0000 0001 zero 0 0000 0000 0000 one step 1 1111 1111 1111 full scale 1 0000 0000 0000 table 3. pcm codes for 1 khz digital milliwatt level sign bit magnitude bits p /8 3 p /8 5 p /8 7 p /8 9 p /8 11 p /8 13 p /8 15 p /8
MC145482 motorola 7 figure 2a. long frame sync (transmit and receive have individual clocking) figure 2b. short frame sync (transmit and receive have individual clocking) figure 2c. signextended (bclkr = 0) transmit and receive both use bclkt, and the first four data bits are the sign bit. fst may occur at a different time than fsr. figure 2d. receive gain adjust (bclkr = 1) transmit and receive both use bclkt. fst may occur at a different time than fsr. bits 14, 15, and 16, clocked into dr, are used for attenuation control for the receive analog output. dr dr don't care 8 dr 7 6 5 4 3 2 1 dr don't care don't care 8 7 6 5 4 3 2 1 13 7 6 5 4 3 2 1 dt dt bclkt fst (fsr) short or long frame sync dt bclkt (bclkr) fst (fsr) dt bclkt (bclkr) fst (fsr) don't care don't care don't care don't care don't care 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 16 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 910111213 8 910 111213 8 9 10 11 12 13 9 10 11 12 15 16 13 8 7 6 5 4 3 2 1 12 11 10 9 bclkt fst (fsr) short or long frame sync figure 2. digital timing modes for the pcm data interface
MC145482 motorola 8 printed circuit board layout considerations the MC145482 is manufactured using highspeed cmos vlsi technology to implement the complex analog signal processing functions of a pcm codecfilter. the fullydiffer- ential analog circuit design techniques used for this device result in superior performance for the switched capacitor fil- ters, the analogtodigital converter (adc) and the digital toanalog converter (dac). special attention was given to the design of this device to reduce the sensitivities of noise, including power supply rejection and susceptibility to radio frequency noise. this special attention to design includes a fifth order lowpass filter, followed by a third order highpass filter whose output is converted to a digital signal with greater than 75 db of dynamic range, all operating on a single 5 v power supply. this results in an lsb size for small audio sig- nals of about 386 m v. the typical idle channel noise level of this device is less than one lsb. in addition to the dynamic range of the codecfilter function of this device, the input gainsetting op amp has the capability of greater than 35 db of gain intended for an electret microphone interface. this device was designed for ease of implementation, but due to the large dynamic range and the noisy nature of the environment for this device (digital switches, radio tele- phones, dsp frontend, etc.) special care must be taken to assure optimum analog transmission performance. pc board mounting it is recommended that the device be soldered to the pc board for optimum noise performance. if the device is to be used in a socket, it should be placed in a low parasitic pin inductance (generally, lowprofile) socket. power supply, ground, and noise considerations this device is intended to be used in switching applica- tions which often require plugging the pc board into a rack with power applied. this is known as ``hotrack insertion.'' in these applications care should be taken to limit the voltage on any pin from going positive of the v dd pins, or negative of the v ss pins. one method is to extend the ground and power contacts of the pcb connector. the device has input protec- tion on all pins and may source or sink a limited amount of current without damage. current limiting may be accom- plished by series resistors between the signal pins and the connector contacts. the most important considerations for pcb layout deal with noise. this includes noise on the power supply, noise generated by the digital circuitry on the device, and cross coupling digital or radio frequency signals into the audio sig- nals of this device. the best way to prevent noise is to: 1. keep digital signals as far away from audio signals as possible. 2. keep radio frequency signals as far away from the audio signals as possible. 3. use short, low inductance traces for the audio circuitry to reduce inductive, capacitive, and radio frequency noise sensitivities. 4. use short, low inductance traces for digital and rf circuitry to reduce inductive, capacitive, and radio frequency radiated noise. 5. bypass capacitors should be connected from the v dd , v ag ref, and v ag pins to v ss with minimal trace length. ceramic monolithic capacitors of about 0.1 m f are acceptable for the v dd and v ag ref pins to decouple the device from its own noise. the v dd capacitor helps supply the instantaneous currents of the digital circuitry in addition to decoupling the noise which may be generated by other sections of the device or other circuitry on the power supply. the v ag ref decoupling capacitor is effecting a lowpass filter to isolate the midsupply voltage from the power supply noise gener- ated onchip, as well as external to the device. the v ag decoupling capacitor should be about 0.01 m f. this helps to reduce the impedance of the v ag pin to v ss at frequencies above the bandwidth of the v ag generator, which reduces the susceptiblility to rf noise. 6. use a short, wide, low inductance trace to connect the v ss ground pin to the power supply ground. the v ss pin is the digital ground and the most negative power supply pin for the analog circuitry. all analog signal processing is referenced to the v ag pin, but because digital and rf circuitry will probably be powered by this same ground, care must be taken to minimize high frequency noise in the v ss trace. depending on the application, a double sided pcb with a v ss ground plane connecting all of the digital and analog v ss pins together would be a good grounding method. a multilayer pc board with a ground plane connecting all of the digital and analog v ss pins together would be the optimal ground configuration. these methods will result in the lowest resistance and the lowest inductance in the ground circuit. this is important to reduce voltage spikes in the ground circuit resulting from the high speed digital current spikes. the magnitude of digitally induced voltage spikes may be hundreds of times larger than the analog signal the device is required to digitize. 7. use a short, wide, low inductance trace to connect the v dd power supply pin to the 5 v power supply. depending on the application, a doublesided pcb with v dd bypass capacitors to the v ss ground plane, as described above, may complete the low impedance coupling for the power supply. for a multilayer pc board with a power plane, connecting all of the v dd pins to the power plane would be the optimal power distribution method. the integrated circuit layout and packaging considerations for the 5 v v dd power circuit are essentially the same as for the v ss ground circuit. 8. the v ag pin is the reference for all analog signal processing. in some applications the audio signal to be digitized may be referenced to the v ss ground. to reduce the susceptibility to noise at the input of the adc section, the threeterminal op amp may be used in a differential to singleended circuit to provide level conversion from the v ss ground to the v ag ground with noise cancellation. the op amp may be used for more than 35 db of gain in microphone interface circuits, which will require a compact layout with minimum trace lengths as well as isolation from noise sources. it is recom- mended that the layout be as symmetrical as possible to avoid any imbalances which would reduce the noise cancelling benefits of this differential op amp circuit. refer to the application schematics for examples of this circuitry.
MC145482 motorola 9 if possible, reference audio signals to the v ag pin instead of to the v ss pin. handset receivers and tele- phone line interface circuits using transformers may be audio signal referenced completely to the v ag pin. re- fer to the application schematics for examples of this circuitry. the v ag pin cannot be used for esd or line protection.
MC145482 motorola 10 maximum ratings (voltages referenced to v ss pin) rating symbol value unit dc supply voltage v dd 0.5 to 6 v voltage on any analog input or output pin v ss 0.3 to v dd + 0.3 v voltage on any digital input or output pin v ss 0.3 to v dd + 0.3 v operating temperature range t a 40 to + 85 c storage temperature range t stg 85 to +150 c power supply (t a = 40 to + 85 c) characteristics min typ max unit dc supply voltage 4.75 5.0 5.25 v active current dissipation (v dd = 5 v) (no load, pi v dd 0.5 v) (no load, pi v dd 1.5 v) e e 5.0 5.2 e e ma powerdown current (v ih for logic levels pdi = v ss must be v dd 0.5 v) fst and fsr = v ss , pdi = v dd e e 0.001 0.01 e e ma digital levels (v dd = 4.75 to 5.25 v, v ss = 0 v, t a = 40 to + 85 c) characteristics symbol min max unit input low voltage v il e 0.6 v input high voltage v ih 2.4 e v output low voltage (dt pin, i ol = 2.5 ma) v ol e 0.4 v output high voltage (dt pin, i oh = 2.5 ma) v oh v dd 0.5 e v input low current (v ss v in v dd ) i il 10 + 10 m a input high current (v ss v in v dd ) i ih 10 + 10 m a output current in high impedance state (v ss dt v dd ) i oz 10 + 10 m a input capacitance of digital pins (except dt) c in e 10 pf input capacitance of dt pin when highz c out e 15 pf
MC145482 motorola 11 analog electrical characteristics (v dd = 4.75 to 5.25 v, v ss = 0 v, t a = 40 to + 85 c) characteristics min typ max unit input current ti+, ti e 0.1 1.0 m a input resistance to v ag (v ag 0.5 v v in v ag + 0.5 v) ti+, ti 10 e e m w input capacitance ti+, ti e e 10 pf input offset voltage of tg op amp ti+, ti e e 5 mv input common mode voltage range ti+, ti 1.2 v dd 1.2 v input common mode rejection ratio ti+, ti e tbd e db gain bandwidth product (10 khz) of tg op amp (r l 10 k w ) e 3000 e khz dc open loop gain of tg op amp (r l 10 k w ) e 95 e db equivalent input noise (cmessage) between ti+ and ti at tg e 30 e dbrnc output load capacitance for tg op amp 0 e 100 pf output voltage range for tg (r l = 2 k w to v ag ) 0.5 e v dd 0.5 v output current (0.5 v v out v dd 0.5 v) tg, ro 1.0 e e ma output load resistance to v ag tg, ro 2 e e k w output impedance ro e 1 e w output load capacitance ro 0 e 500 pf dc output offset voltage of ro referenced to v ag e e 25 mv v ag output voltage referenced to v ss (no load) v dd /2 0.1 v dd /2 v dd /2 + 0.1 v v ag output current with 25 mv change in output voltage 2.0 10 e ma power supply rejection ratio transmit (0 to 100 khz @100 mvrms applied to v dd , receive cmessage weighting, all analog signals referenced to v ag pin) tbd tbd tbd tbd e e dbc power drivers pi, po+, po input current (v ag 0.5 v pi v ag + 0.5 v) pi e 0.05 1.0 m a input resistance (v ag 0.5 v pi v ag + 0.5 v) pi 10 e e m w input offset voltage pi e e 20 mv output offset voltage of po+ relative to po (inverted unity gain for po) e e 50 mv output current (v ss + 0.7 v po+ or po v dd 0.7 v) 10 e e ma po+ or po output resistance (inverted unity gain for po) e 1 e w gain bandwidth product (10 khz, open loop for po) e 1000 e khz load capacitance (po+ or po to v ag , or po+ to po) 0 e 1000 pf gain of po+ relative to po (r l = 300 w , + 3 dbm0, 1 khz) 0.2 0 + 0.2 db total signal to distortion at po+ and po with a differential load of: 300 w 100 nf in series with 20 w 100 w 45 e e 60 40 40 e e e dbc power supply rejection ratio 0 to 4 khz (0 to 25 khz @ 100 mvrms applied to v dd . 4 to 25 khz po connected to pi. differential or measured referenced to v ag pin.) tbd e tbd tbd e e db
MC145482 motorola 12 analog transmission performance (v dd = 4.75 to 5.25 v, v ss = 0 v, all analog signals referenced to v ag , 0 dbm0 = 0.775 vrms = 0 dbm @ 600 w , fst = fsr = 8 khz, bclkt = mclk = 2.048 mhz synchronous operation, t a = 40 to + 85 c, unless otherwise noted) ch i i a/d d/a ui characteristics min typ max min typ max units peak single frequency tone amplitude without clipping t max e 1.575 e e 1.575 e vpk absolute gain (0 dbm0 @ 1.02 khz, t a = 25 c, v dd = 5.0 v) 0.25 e + 0.25 0.25 e + 0.25 db absolute gain variation with temperature 0 to + 70 c 40 to + 85 c e e tbd tbd e e e e tbd tbd e e db absolute gain variation with power supply (t a = 25 c) e tbd e e tbd e db total distortion, 1.02 khz tone (cmessage weighting) + 3 dbm0 0 dbm0 10 dbm0 20 dbm0 30 dbm0 40 dbm0 50 dbm0 60 dbm0 e e e e e e e e 55 58 58 53 44 34 24 14 e e e e e e e e e e e e e e e e 60 60 60 55 46 36 26 16 e e e e e e e e dbc idle channel noise (for endtoend and a/d, see note 1) (cmessage weighted) (psophometric weighted) e e e e 17 69 e e e e 11 79 dbr nc0 dbm0p frequency response 15 hz (relative to 1.02 khz @ 0 dbm0) (hb = 0) 50 hz 60 hz 165 hz 200 hz 300 to 3000 hz 3300 hz 3400 hz 3600 hz 4000 hz 4600 hz to 100 khz e e e e 1.0 0.20 0.35 0.9 e e e e e e 3 e e e e 3 e e 40 30 26 e 0.4 + 0.20 + 0.20 0 e 14 32 0.5 0.5 0.5 0.5 0.5 0.20 0.35 0.9 e e e e e e e e e e e 3 e e 0 0 0 0 0 + 0.20 + 0.20 0 e 14 30 db outofband spurious at v ag ref (300 to 3400 hz @ 0 dbm0 in) 4600 to 7600 hz 7600 to 8400 hz 8400 to 100,000 hz e e e e e e e e e e e e e e e 30 40 30 db idle channel noise selective (8 khz, input = v ag , 30 hz bandwidth) e e e e e 70 dbm0 absolute delay (1600 hz) (hb = 0) e e 315 e e 205 m s group delay referenced to 1600 hz (hb = 0) 500 to 600 hz 600 to 800 hz 800 to 1000 hz 1000 to 1600 hz 1600 to 2600 hz 2600 to 2800 hz 2800 to 3000 hz e e e e e e e e e e e e e e 210 130 70 35 70 95 145 40 40 40 30 e e e e e e e e e e e e e e 85 110 175 m s crosstalk of 1020 hz @ 0 dbm0 from a/d or d/a (note 2) e e 75 e e 75 db notes: 1. extrapolated from a 1020 hz @ 50 dbm0 distortion measurement to correct for encoder enhancement. 2. selectively measured while stimulated with 2667 hz @ 50 dbm0.
MC145482 motorola 13 digital switching characteristics, long frame sync and short frame sync (v dd = 4.75 to 5.25 v, v ss = 0 v, all digital signals referenced to v ss , t a = 40 to + 85 c, c l = 150 pf, fst = fsr = 8 khz, unless otherwise noted) ref. no. characteristics min typ max unit 1 master clock frequency for mclk e e e e e e e 256 512 1536 1544 2048 2560 4096 e e e e e e e khz 1 mclk duty cycle for 256 khz operation 45 e 55 % 2 minimum pulse width high for mclk (frequencies of 512 khz or greater) 50 e e ns 3 minimum pulse width low for mclk (frequencies of 512 khz or greater) 50 e e ns 4 rise time for all digital signals e e 50 ns 5 fall time for all digital signals e e 50 ns 6 setup time from mclk low to fst high 50 e e ns 7 setup time from fst high to mclk low 50 e e ns 8 bit clock data rate for bclkt or bclkr 256 e 4096 khz 9 minimum pulse width high for bclkt or bclkr 50 e e ns 10 minimum pulse width low for bclkt or bclkr 50 e e ns 11 hold time from bclkt (bclkr) low to fst (fsr) high 20 e e ns 12 setup time for fst (fsr) high to bclkt (bclkr) low 80 e e ns 13 setup time from dr valid to bclkr low 0 e e ns 14 hold time from bclkr low to dr invalid 50 e e ns long frame specific timing 15 hold time from 2nd period of bclkt (bclkr) low to fst (fsr) low 50 e e ns 16 delay time from fst or bclkt, whichever is later, to dt for valid msb data e e 60 ns 17 delay time from bclkt high to dt for valid data e e 60 ns 18 delay time from the later of the 13th (16th for signextended mode) bclkt falling edge, or the falling edge of fst to dt output high impedance 10 e 60 ns 19 minimum pulse width low for fst or fsr 50 e e ns short frame specific timing 20 hold time from bclkt (bclkr) low to fst (fsr) low 50 e e ns 21 setup time from fst (fsr) low to msb period of bclkt (bclkr) low 50 e e ns 22 delay time from bclkt high to dt data valid 10 e 60 ns 23 delay time from the 13th (16th for signextended mode) bclkt low to dt output high impedance 10 e 60 ns
MC145482 motorola 14 mclk dt fst bclkt 7 11 15 16 3 17 4 8 9 10 18 18 16 12 6 2 1 5 bclkr (bclkt) dr fsr 12 3 4 5 6 13 123456 13 14 13 8 9 10 12345671314 12345671314 15 12 11 figure 3. long frame sync timing
MC145482 motorola 15 mclk dt fst bclkt 7 12 3 22 4 8 9 10 23 22 11 6 2 1 5 bclkr dr fsr 1234 56 13 123456 13 14 13 8 9 10 12345671314 12345671314 12 11 20 21 20 21 figure 4. short frame sync timing
MC145482 motorola 16 pcm in 2.048 mhz pcm out 8 khz 1.0 m f + 5 v 0.1 m f 0.01 m f 10 k w analog in pdi ro pi po po+ bclkr dr fsr v dd v ag ref hb mclk bclkt dt fst tg ti ti+ v ag v ss 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 10 k w 10 k w 10 k w 1.0 m f audio out + 0.1 m f 2x20 k figure 5. MC145482 test circuit e signals referenced to v ag pin pcm in 2.048 mhz pcm out 8 khz 1.0 m f + 5 v 0.1 m f 0.01 m f 10 k w 10 k w 10 k w 10 k w analog in 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 1.0 m f pdi ro pi po po+ bclkr dr fsr v dd v ag ref hb mclk bclkt dt fst tg ti ti+ v ag v ss + 68 m f r l 2 k w audio out 10 k w r l 150 w audio out 2x20 k 0.1 m f figure 6. MC145482 test circuit e signals referenced to v ss
MC145482 motorola 17 sidetone 420 pf 420 pf rec mic 68 m f +3 v pcm in 2.048 mhz pcm out 8 khz 0.1 m f + 5 v 0.1 m f 0.01 m f 75 k w 1 k w 75 k w pdi ro pi po po+ bclkr dr fsr v dd v ag ref hb mclk bclkt dt fst tg ti ti+ v ag v ss 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 0.1 m f 1 k w 1 k w 1 k w 0.1 m f figure 7. MC145482 handset interface 48 v n = 0.5 r0 = 600 w n = 0.5 ring tip 1/4 r0 pcm in 2.048 mhz pcm out 8 khz 1.0 m f + 5 v n = 0.5 10 k w pdi ro pi po po+ bclkr dr fsr v dd v ag ref hb mclk bclkt dt fst tg ti ti+ v ag v ss 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 0.1 m f 20 k w 0.1 m f 2x20 k 0.1 m f figure 8. MC145482 stepup transformer line interface
MC145482 motorola 18 package dimensions dw suffix sog package case 751d04 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 sd suffix ssop case 940c02 20 11 10 1 h a b p r notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per ansi y14.5m, 1982. 3. dimensions a and b do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the lead width dimension. dim min max min max inches millimeters a 7.10 7.30 0.280 0.287 b 5.20 5.38 0.205 0.212 c 1.75 1.99 0.069 0.078 d 0.25 0.38 0.010 0.015 f 0.65 1.00 0.026 0.039 g 0.65 bsc 0.026 bsc h 0.59 0.75 0.023 0.030 j 0.10 0.20 0.004 0.008 l 7.65 7.90 0.301 0.311 m 0 8 0 8 n 0.05 0.21 0.002 0.008 g d s p m 0.120 (0.005) t 0.076 (0.003) n c m r m 0.25 (0.010) l j f m note 4
MC145482 motorola 19 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://www.mot.com/sps/ MC145482/d ?

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